CMOS FETs are universally employed in electronic circuit applications, such as signal processing, computing, and wireless communications as non-limiting examples. Scaling down to smaller dimensions the gate length of both N-channel FETs (NETs) and P-channel FETs (PFETs) in CMOS circuits leads to increased CMOS circuit speed. However, detrimental short-channel effects lead to high off-state leakage currents in CMOS devices, thereby increasing the power consumption. In a case of extreme short-channel effects, CMOS circuits fail to operate.
Halo doping is a commonly used technique in the industry to minimize short-channel effects (SCEs). FIGS. 1a and 1b show across-section of conventional halo-doped FETs on SOI wafers and bulk Si wafers, respectively. Halo doping, however, leads to the following well known problems:
1. Halo doping introduces ionized impurities in the channel region that lead to degradation of carrier mobility in the MOSFET inversion layer.
2. Statistical fluctuations in the number of halo dopant atoms, commonly referred to as random dopant fluctuations, increase as the halo doping density is increased and can result in large variations in threshold voltage. This problem is particularly troublesome for static random access memory (SRAM) transistors and could potentially lead to SRAM failure.3. Halo doping causes partial compensation of the source/drain extension regions, thereby increasing the FET external series resistance.
The SSRW FET is a device geometry with an undoped channel and a heavily-doped laterally-uniform ground plane that is expected to exhibit better short-channel control, better carrier transport properties, lower threshold voltage variations, and lower parasitic series resistance than conventional halo-doped devices on either SOI or bulk Si substrate. For the SSRW FET, the presence of a heavily-doped ground plane leads to significantly improved SCEs as compared to conventional halo-doped devices. In the SSRW FET, there is no need for halo doping as the ground plane fulfills the function of controlling SCEs and avoids the above-identified halo doping problems.
Prior art methods of fabricating SSRW FETs suffer from various problems, and the resultant transistors do not demonstrate the expected benefits of SSRW FETs. The following properties of the SSRW structure are now well established.
1. SSRW FETs with a proper choice of undoped channel thickness and ground-plane doping exhibit superior short channel effects as compared to conventional halo-doped devices on either SOI or bulk Si substrates.
2. SSRW FETs should not suffer from degradation of carrier mobility in the MOSFET inversion layer since the channel region is undoped or very lightly doped (≦1016 cm−3 surface doping concentration) and, therefore, the channel is substantially free of ionized impurities.3. SSRW FETs should not suffer from large variations in threshold voltage due to random dopant fluctuations because the channel region is undoped, and the heavily-doped ground plane is away from the surface region.4. SSRW FETs should not suffer from an increase in FET external series resistance because there are no halo implants to compensate the source/drain extension regions.
Additionally, some other desirable properties for MOSFETs are mentioned below.
5. CMOS devices should have low junction leakage current in order to reduce net transistor off-state current, thereby reducing CMOS circuit power consumption.
6. CMOS devices should have low deep source/drain-to-well junction capacitance in order to reduce parasitic capacitance, thereby increasing CMOS circuit speed.
U.S. Pat. No. 6,423,601 B1 (Ishida et al.) teaches the use of nitrogen and boron co-implants for forming p-type well region for NFETs with a parabolically-shaped dopant concentration profile. While a parabolically-shaped dopant profile will provide the benefit of a punch-through stopper for CMOS on bulk Si substrates, it is not sharp enough to reduce short-channel channel effects in CMOS transistors with gate lengths below 30 nm, and therefore, does not satisfy property (1) mentioned above.
U.S. Pat. No. 7,199,430 B2 (Babcock et al.) teaches the use of laterally-uniform carbon containing layers or carbon halo co-implants to prevent diffusion of well implants into the channel region. As is stated in the claims, the carbon-containing layers must contain at least 0.1 atomic percent of carbon, that is, the carbon concentration must be greater than 5×1019 cm−3. It is well known that a high dose of impurity concentration near the deep source/drain region leads to large junction leakage current, thereby increasing the net off-state leakage current of CMOS devices and thus fails to satisfy property (5) mentioned above.
U.S. Patent Application 2007/0128820 A1 (Majumdar et al) describes a method for forming a self-aligned retrograde well using a removable gate process flow in order to reduce junction capacitance and junction leakage current. This method involves high-energy ion implantation for creating a retrograde well. It is well known that high-energy implants have large vertical straggle, and therefore, will not lead to a super-steep retrograde well implant profile. This method, therefore, fails to satisfy property (1) mentioned above. Furthermore, a removable gate process for gate lengths below 30 nm could also lead to low device and circuit yield due to problems with gap fill for gap sizes below 30 nm.
U.S. Pat. No. 6,881,987 B2 (Sohn) describes a retrograde well PFET structure on bulk Si wafers and provides a method for making same that leads to surface doping concentration Cs˜1×1017 cm−3, as shown herein in FIG. 1c (which reproduces FIG. 5 of the patent).
U.S. Pat. Nos. 6,927,137 B2 (Chakravarthi et al.) and 7,061,058 B2 (Chakravarthi et al.) describe a method for fabricating retrograde well NFETs. The method involves conventional boron p-well formation and the use of hydrogen implants in the gate dielectric layer to attract boron near the surface into the gate dielectric layer during a subsequent source/drain activation anneal. This method leads to surface doping concentration Cs˜1×1018 cm−3, as shown herein in FIG. 1d, which reproduces FIG. 2 of the patent).
A surface doping concentration Cs˜1017-1018 cm−3 achieved using the methods in U.S. Pat. Nos. 6,881,987 B2 (Sohn), 6,927,137 B2 (Chakravarthi et al.), and 7,061,058 B2 (Chakravarthi et al.) is lower than that achieved in conventional halo-doped devices, but not sufficiently low to realize a substantial mobility benefit because at least significant ionized impurity scattering. These methods, therefore, fail to satisfy property (2) mentioned above.
U.S. Pat. No. 6,881,641 B2 (Wieczorek et al.) describes a retrograde well FET structure on a bulk Si wafer where “an epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure”. This patent describes the formation of the well region after STI formation: “After formation of the shallow trench isolation 302, the P-well structure 310 and the N-well structure 320 are defined by ion implantation”. This implies that the channel region is epitaxially grown after STI formation.
U.S. Pat. No. 7,002,214 B1 (Boyd et al.) describes a retrograde well FET structure on ultra-thin SOI substrates, where an undoped, epitaxial Si cap is formed after retrograde well ion implantation and STI formation. The process flow, shown herein in FIG. 1e, which reproduces FIG. 4 of the patent, is not suitable for maintaining the steepness of retrograde well implant profiles seen in FIG. 1f, which reproduces FIG. 6 found in: Z. Ren, M. Ieong, J. Cai, J. Holt, D. Boyd, R. Mo, H. Yin, O. Dokumaci, S. Kawanaka, T. Sato, P. Ronsheim, J. Wang, C. Y. Sung, and W. Haensch, “Selective epitaxial channel ground plane thin SOI CMOS devices”, IEDM Technical Digest, December 2005.
Both U.S. Pat. Nos. 6,881,641 B2 (Wieczorek et al.) and 7,002,214 B1 (Boyd et al.) provide a method for fabricating retrograde well FETs where the Si cap epitaxy is performed after STI formation. However, performing Si cap epitaxy after STI formation leads to Si cap thickness non-uniformity, which in turn acts as another source of variation and can result in large variations in transistor threshold voltage. These methods, therefore, fail to satisfy property (3) mentioned above. Furthermore, Si epitaxy on narrow width devices, such as those used in SRAMs, leads to faceted growth due to differential growth rates on different crystallographic orientations, as shown schematically in FIG. 1g. This leads to high electric fields underneath the gate electrode near the STI edge and a large leakage current, thereby increasing the net off-state leakage current of CMOS devices.
None of the foregoing US patents and the publication describe a retrograde well FET structure and method for forming the same that satisfies all the generally established advantages of the SSRW structure (properties 1-4 mentioned above) and that also satisfies basic desired properties of CMOS transistors in CMOS circuits (properties 5 and 6 mentioned above). It would thus be highly desirable to provide a method of making SSRW CMOS devices that satisfy all the above mentioned desirable properties of SSRW FETs and CMOS FETs (properties 1-6 mentioned above).